NASA’s Jet Propulsion Lab (JPL) has selected Microchip to design and manufacture the multi-core High Performance Spaceflight Computer (HPSC) microprocessor based on SiFive’s eight RISC-V X280 cores with vector processing instruction expansions organized into two groups , with four additional RISC-V cores added for general-purpose computing. The operational goal of the project is to develop “flight computing technology that will provide at least 100 times the computing capability of current spaceflight computers”. In a talk at the recent RISC-V Summit, HPSC Leadership Team Member and JPL Consultant Pete Fiacco explained the overall goals of the HPSC program.
Despite its name, the HPSC is not strictly speaking a SoC processor for space. It is designed to be a reliable computer for a variety of applications on Earth – such as defense, commercial aviation, industrial robotics and medical equipment – as well as being a good candidate for use in government spacecraft. and commercial. Besides computing capacity, three characteristics that HPSC needs are fault tolerance, radiation tolerance, and overall platform security. The project will result in the development of the HPSC chip, boards, software stack, and reference designs with initial availability in 2024 and space-qualified hardware available in 2025. Fiacco said that whatever NASA JPL will do in the future will be based on the HPSC.
NASA’s JPL set the objectives of the HPSC based on its mission requirements to provide autonomy for future spacecraft. Simply put, the tasks associated with autonomy are sensing, perceiving, deciding, and acting. Detection involves remote imaging using multispectral sensors and image processing. Perception gives meaning to captured data using additional image processing. Decision making includes mission planning that incorporates the current and future direction of the vehicle. Actuation involves orbital and surface maneuvers as well as the activation and management of experiments.
Correlating these tasks with NASA’s overall goals for its missions, Fiacco explained that the HPSC is designed to allow space equipment to go, land, live and explore extraterrestrial environments. Spacecraft must also report to Earth, which is why Fiacco has also included communications in the four main tasks. All of this will require a huge leap in computing power. Simulations suggest that the HPSC increases computing performance by 1,000 times over processors currently flying in space, and Fiacco expects that number to improve with further optimization of the HPSC’s software stack.
It’s hard to describe how the HPSC represents an upgrade for NASA’s JPL computing platform without pitting the new machine against computers currently running off-planet. For example, the essentially similar nuclear-powered Curiosity and Perseverance rovers that currently circle Mars with semi-autonomy are based on BAE Systems’ RAD750 microprocessors. (To see “Baby you can drive my Rover. The RAD750 uses the 32-bit PowerPC 750 architecture and is manufactured with a radiation-tolerant semiconductor process. This chip has a maximum clock frequency of 200 MHz and represents the best of computer architecture circa 2001. More than 150 RAD750 processors are said to have been launched into space. Remember, NASA likes to fly stuff that’s been flown before. One of the latest space artifacts to carry an RAD750 into space is the James Webb Space Telescope (JWST), which is now viewing the universe in the infrared spectrum and collecting massive amounts of new astronomical data while sitting on a Lagrange orbit at a million kilometers. From land. (That’s four times larger than the orbit of the moon.) The JWST’s RAD750 processor runs at 118 MHz.
Our other great space observatory, the solar-powered Hubble Space Telescope (HST), has an even older processor. The HST payload computer is an 18-bit NASA Standard Spacecraft Computer-1 (NSSC-1) system built in the 1980s but designed even earlier. This payload computer controls and coordinates the data streams of the various HST science instruments and monitors their status. (To see “Lose Hubble – Save Hubble. »
The original NSSC-1 computer was developed by NASA’s Goddard Space Flight Center and Westinghouse Electric in the early 1970s. The design is so old that it is not microprocessor-based. The initial version of this computer incorporated 1700 DTL flat ICs from Fairchild Semiconductor and used magnetic core memory. Long before the launch of the HST in 1990, the design of the NSSC-1 processor was “improved” to accommodate some of the earliest MSI TTL gate arrays, each incorporating around 130 logic gates.
I’m not a spatial computing expert, so I asked an expert for his opinion. The person I know most familiar with spatial computing with microprocessors and FPGAs is my friend Adam Taylor, founder and chairman of Adiuvo Engineering in the UK. I asked Taylor what he thought of HPSC and he wrote:
“The HPSC is actually quite exciting for me. We do a lot in space and the computation is a challenge. Many current computing platforms are based on older architectures such as SPARC (LEON series) or Power PC (RAD750 / RAD5545). Not only these [processors] have less computing power, they also have ecosystems that are limited. Limited ecosystems mean longer development times (less reuse, more “fighting” with tools as they are generally less polished) and they also limit the attraction of new talent, people who want to work with frameworks, modern processors and tools. It also limits the pool of experienced talent (which is a growing problem as it is in many industries).
“Creating a high-performance multi-core processor based on RISC-V will open up a vast ecosystem of tools and frameworks while attracting new talent and expanding the pool of experienced talent. The processors themselves seem very interesting because they are designed with high performance in mind so they have SIMD/vector processing and AI (urgh such an over the top buzzword) It also seems like they have given power management some serious consideration, which which is essential for different applications, especially in space.
“It is interesting that as an FPGA design company (primarily) we have designed in several MicroChip SAM71 RT and RH [radiation tolerant and radiation hardened] microcontrollers recently, which really offer great capabilities where processing demands are low. I see HPSC as very complementary to this line of devices, leaving ultra-high performance/real-time applications very difficult to implement in the FPGA. Ultimately, HPSC gives engineers another tool to choose from, and it’s designed to prevent the all-too-common starting-from-scratch approach that engineers love. Unfortunately, this approach always increases the cost and technical risk on these projects, and we’ve had enough of that already.
One final note: During my research for this article, I discovered that NASA’s HPSC was not always based on the RISC-V architecture. A presentation given at the Radiation Hardened Electronics Technology (RHET) conference in 2018 by Wesley Powell, Deputy Chief of Technology in the Electrical Engineering Division at NASA’s Goddard Space Flight Center, includes a block diagram of the HPSC, which shows an earlier conceptual design based on eight Arm Cortex-A53 microprocessor cores with NEON SIMD vector engines and floating-point units. Powell continues to be the lead technologist for the HPSC program. At some point in the evolution of HPSC over the past four years, at least in late 2020, when NASA released a Small Business Innovation Research (SBIR) Project Phase I solicitation for HPSC, cores Arm processor cores had been replaced with a requirement for RISC-V processor cores. This change was officially cast in stone last September with the announcement of project pricing to Microchip and SiFive. A sign of the times, perhaps?
Related