Taipei, Taiwan, 01 Feb. 2023 (GLOBE NEWSWIRE) — Alchip Technologies is bolstering its role as a founding member of TSMC’s 3DFabric™ alliance by enhancing its 3nm process technology and advanced packaging capabilities.
The company supports the foundry initiative, announced in late October, viewing it as a market driver that will deliver Alchip’s most advanced high-performance computing ASIC technology to edge customer applications.
TSMC’s 3DFabric is a complete family of advanced 3D silicon stacking and packaging technologies that unleash customer innovation in the system-level approach. It consists of TSMC or TSMC-SoIC™ (system on integrated chips) front-end technologies, dedicated fabs for 3D stacked die assembly and testing, and TSMC 3DFabric back-end technologies include the family of packaging technologies CoWoS and InFO.
The TSMC 3DFabric Alliance is the latest addition to TSMC’s Open Innovation Platform (OIP). New alliance partners have early access to TSMC’s 3DFabric technologies, allowing them to develop and optimize their solutions in parallel with TSMC. This gives customers early availability of EDA, IP, memory, outsourced semiconductor assembly and testing (OSAT), substrate and testing.
“As a leader in high-performance computing ASICs, Alchip’s participation in the TSMC 3DFabric Alliance is imperative,” said Johnny Shen, President and CEO of Alchip Technologies. “This new initiative reinforces TSMC’s leadership in the semiconductor space by providing strategic opportunities for advanced, high-performance ASIC companies to extend their most advanced packaging capabilities to innovative technology customers.”
Alchip supported 3nm customer ASIC designs and registered its first test chip in January 2023. It became the first dedicated high-performance ASIC company to announce full readiness of the design ecosystem and production targeting TSMC’s latest N3E process technology.
On the advanced packaging front, Alchip is fine-tuning its safer chip-on-substrate (CoWoS®) packaging capability. CoWoS improves overall chip interconnect density and performance and is essential for nearly all high-performance computing (HPC) ASICs.
CoWoS is a wafer-level 2.5D multi-chip packaging technology that integrates a side-by-side chip on a silicon interposer. Micro-bumps bond individual chips to a silicon spacer, forming a chip-on-wafer. The packaging is completed by bonding to a packaging substrate.
CoWoS chipsets include a high-performance system-on-chip (SoC) and a high-performance memory block (HBM3 or HBM2E). Alchip’s CoWoS service covers all types of CoWoS packages such as CoWoS-S, CoWoS-R and CoWoS-L.
For more information about Alchip, visit www.alchip.com
About Alchip
Alchip Technologies Ltd., founded in 2003 and headquartered in Taipei, Taiwan, is a leading global supplier of silicon and design and production services for system companies developing complex, high-volume ASICs and SoCs. The company provides faster and more cost-effective solutions for SoC design at mainstream and advanced levels, including 7nm, 6nm, 5nm and 4nm processes. Alchip has built its reputation as a leader in high performance ASICs through its advanced 2.5D/3D package services, CoWoS/chiplet design and manufacturing experience. Customers include world leaders in AI, HPC/supercomputing, mobile phones, entertainment devices, networking equipment and other electronic product categories. Alchip is listed on the Taiwan Stock Exchange (TWSE: 3661), is a TSMC Certified Value Chain Aggregator and is a founding member of the new TSMC 3DFabric Alliance®.
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Examples of CoWoS Chipsets